Further VHDL features, particularly in the field of behavioral modeling techniques. Introduction to logic synthesis from Register transfer level description level.
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| Written exam: | 100 | % | Project submission: | % | |
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| Type of teaching activity | Content, sequencing and organisation |
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| Course | Revision and new concepts of VHDL hardware description language : Register, FSM, generic structure Design Methodology: project achitecture, dedicated text editor, scripting methodology Synthesis design flow from RTL description level to post synthesis gate level simulation Advanced testbench modelling : file managing, assert based simulation Design reuse, arithmetic modelling, counter based structures Applications through a complete example with industrial CAD tools. Post synthesis simulation. |