Understanding and implementing the fundamental concepts of a material description language allowing the design of large scale digital systems: VHDL (VHSIC Hardware Description Language), with the help of a class course followed by project work. Four course sessions and supervised study classes will cover the key notions: design units, libraries, concurrent processes, signals and variables, simulation paradigms, modelling by structural or behavioural data streams, configuration, test-benches, genericity, description of finite state machines (type Moore and Mealy).
Five project sessions will apply these notions to the design of an algorithm for symmetric encryption by AES (Advanced Encryption Standard) blocks.
| On completion of the unit, the student will be capable of: | Classification level | Priority |
|---|---|---|
| Mastering the fundamental notions and major concepts of material description language using VHDL | 2. Understand | Essential |
| Exploiting these notions in the use of modelling tools and simulation of digital systems | 3. Apply | Essential |
| Designing a complex integrated digital system | 7. Create | Essential |
| Percentage ratio of individual assessment | Percentage ratio of group assessment | ||||
|---|---|---|---|---|---|
| Written exam: | % | Project submission: | % | ||
| Individual oral exam: | % | Group presentation: | % | ||
| Individual presentation: | % | Group practical exercise: | % | ||
| Individual practical exercise: | % | Group report: | % | ||
| Individual report: | 100 | % | |||
| Other(s): % | |||||
| Type of teaching activity | Content, sequencing and organisation |
|---|---|
| Course/Supervised study | Structural type description / Configuration management / Testbench / Supervised study class on modelling tools |
| Course/Supervised study | Behavioural type description / Explicit, signal and variable processes / Supervised study class on modelling tools |
| Course/Supervised study | Principles of Moore and Mealy finite state machines and their modelling with VHDL |
| Project | Design project for an algorithm for symmetric encryption by AES (Advanced Encryption Standard) blocks. |