Course unit

Processor Architecture

Last updated: 26/09/2022

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Course Director(s):

RIGAUD Jean-Baptiste

General Description:

An introduction to processor architecture via. a material approach in which  DLX monocycle and multi-cycle architecture is reviewed to discover the notions of pipeline. The memory hierarchy is then studied. The software aspects with MIPS processors such as ABI and linking phases, are then presented.

Key words:

Pipeline Instructional game Memory architecture

Number of teaching hours

21

Fields of study

Teaching language

French

Intended learning outcomes

On completion of the unit, the student will be capable of: Classification level Priority

Learning assessment methods

Percentage ratio of individual assessment Percentage ratio of group assessment
Written exam: 100 % Project submission: %
Individual oral exam: % Group presentation: %
Individual presentation: % Group practical exercise: %
Individual practical exercise: % Group report: %
Individual report: %
Other(s): %

Programme and content

Type of teaching activity Content, sequencing and organisation
Course/Supervised study

Introduction to microprocessor architecture

DLX Monocycle architecture

DLX Multicycles and Pipelines

Memory hierarchy

MIPS software aspects : ABI, CRT and linking phases