Understanding and implementing the fundamental concepts of a hardware description language enabling the design of large scale digital systems, in this case VHDL (VHSIC Hardware Description Language), with the help of a course followed by project work.
Four sessions of courses and supervised studies will cover the key notions: design units, libraries, concurrent processes, signals and variables, simulation paradigms; modelling by data streaming, either structural or behavioural, configurations, testbenches, genericity and description of finite state machines of the Moore and Mealy type.
Five sessions of project work will apply these notions to the design of a symmetric encryption block using AES (Advanced Encryption Standard).
| On completion of the unit, the student will be capable of: | Classification level | Priority |
|---|---|---|
| Mastering the fundamental notions and major concepts of hardware description languages through VHDL | 2. Understand | Essential |
| Exploiting these notions to use modelling and simulation tools of digital systems | 3. Apply | Essential |
| Designing a complex integrated digital system | 7. Create | Essential |
| Percentage ratio of individual assessment | Percentage ratio of group assessment | ||||
|---|---|---|---|---|---|
| Written exam: | 100 | % | Project submission: | 50 | % |
| Individual oral exam: | 0 | % | Group presentation: | 25 | % |
| Individual presentation: | 0 | % | Group practical exercise: | 25 | % |
| Individual practical exercise: | 0 | % | Group report: | 0 | % |
| Individual report: | 0 | % | |||
| Other(s): 0 % | |||||
| Type of teaching activity | Content, sequencing and organisation |
|---|---|
| Course/Supervised study | Principles of hardware system modelling languages Fundamental notions of VHDL: design units, processes, signals, concurrent and sequential instructions Simulation paradigms; discrete events, transactions, inertial delays, glitches Libraries and packages Data flow type descriptions Supervised study of modelling tools (Modelsim) |